High-performance hardware architectures for multi-level lifting-based discrete wavelet transform

EURASIP Journal on Image and Video Processing

Table 10 Comparison of hardware and time complexity of the proposed PMA for lifting (9, 7) filter

Architecture	Mohanty[14]	Mohanty[21]	Hu[19]	Proposed PMA
Scheme	LT	CV	LT	LT
Multiplier	6Px₃	189	$\frac{105 S}{8} + 6$	32
Adder	32Px₃/3	294	21S+12	64
Registers	N(11x₂ + 10x₅)	$\frac{21 N}{4} + 443$	$3 N + \frac{341 S}{8}$	48
Line buffers	0	0	0	4N + 24N
ACT	$\frac{N^{2}}{P}$	$\frac{N^{2}}{16}$	$\frac{N^{2}}{2 S}$	$\frac{N^{2}}{2} + \sum \frac{N}{2^{2}}$
Critical path delay	2Ta + Tm	≈Tm	Ta + Tm	Ta + Tm

Input image size N × N and j = 3. L.B., line buffer; P, number of samples processed per clock cycle; S, strip size; Ta, adder delay; Tm, multiplier delay; J = min(log₂M,log₂N); x₁ = 2/3 × (1 - 4^-L); x₂ = (1 - 2^-L); x₃ = (1 - 2^-2L).